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M34W02
2Kbit Serial EEPROM with Software Data Protection
PRELIMINARY DATA
TWO WIRE I2C SERIAL INTERFACE SUPPORTS 400kHz PROTOCOL 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE: - 4.5V to 5.5V for M34W02 - 2.5V to 5.5V for M34W02-W - 1.8V to 5.5V for M34W02-R SOFTWARE DATA PROTECTION BYTE and PAGE WRITE (up to 16 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD and LATCH-UP PERFORMANCES
8 1
PSDIP8 (BN) 0.25mm Frame
8 1
SO8 (MN) 150mil Width
8 1
TSSOP8 (DW) 169mil Width
Figure 1. Logic Diagram DESCRIPTION The M34W02 is a 2K bit electrically erasable programmable memory (EEPROM), organized as 256 x 8-bits which includes a Software Data Protection feature. This allows Write Protection of a block of memory with a selectable size and location. By sending the device a specific sequence, it is possible to protect the top or the bottom locations of the memory area. The protection is activated when the WC pin is held high.
VCC
3 E0-E2 SCL WC M34W02 SDA
Table 1. Signal Names
E0-E2 SDA SCL WC VCC VSS Chip Enable Inputs Serial Data Address Input/Output Serial Clock Write Control Supply Voltage Ground
VSS
AI01960
March 1998
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M34W02
Figure 2A. DIP Pin Connections Figure 2B. SO and TSSOP Pin Connections
M34W02 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI01961
M34W02 VCC WC SCL SDA E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI01962
VCC WC SCL SDA
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD Parameter Ambient OperatingTemperature Storage Temperature Lead Temperature, Soldering (PSDIP8 package) (SO8 package) (TSSOP8 package) 10 sec 40 sec t.b.c.
(2)
Value -40 to 85 -65 to 150 260 215 t.b.c. -0.6 to 6.5 -0.3 to 6.5
(3)
Unit C C C V V V V
VIO VCC VESD
Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model)
(4)
4000 500
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Depends on range. 3. MIL-STD-883C, 3015.7 (100pF, 1500 ). 4. EIAJ IC-121 (Condition C) (200pF, 0 ).
DESCRIPTION (cont'd) The M34W02 is manufactured in SGS-THOMSON's Hi-Endurance Advanced CMOS technology. The memories operate with a power supply value as low as 1.8V for the M34W02-R. Plastic Dual In-line, Plastic Small Outline and Thin Shrink Small Outline packages are available. The memory is compatible with the I2C standard, two-wire serial interface which uses a bi-directional data bus and serial clock. The memories carry two built-in 4-bit device identification codes: '1010' which corresponds to the I2C bus definition to access the memory area and '0110' to access the additional Protect Register. These codes are used together with 3 chip enable inputs (E2, E1, E0) so that up to eight 2K bit devices may be attached to
the I2C bus and selected individually. The memory behaves as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code '1010' or '0110' followed by the 3 chip enable bits), plus one read/write bit (RW) and terminated by an acknowledge bit. When writing data to the memory, it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition after an Ack for WRITE and after a NoAck for a READ.
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M34W02
Table 3. Device Select Code
Device Type Identifier Bit Memory Area Device Select Code Protect Register Device Select Code
Note: The MSB b7 is sent first.
Chip Enable b4 0 0 b3 E2 E2 b2 E1 E1 b1 E0 E0
RW b0 RW RW
b7 1 0
b6 0 1
b5 1 1
Table 4. Operating Modes (1)
Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write RW bit '1' '0' '1' '1' '0' '0' WC X X X X VIL VIL
(2) (2)
Bytes 1 1 1 to 256 1 16
Initial Sequence START, Device Select, RW = '1' START, Device Select, RW = '0', Address, reSTART, Device Select, RW = '1' Similar to Current or Random Mode START, Device Select, RW = '0' START, Device Select, RW = '0'
Notes: 1. X = VIH or VIL 2. WC input level is don't care if the data to modify is in a non-write protected area. Read also the 'Write Protection using the Protect Register paragraph.
Power On Reset: VCC lock out write protect. In order to prevent any possible data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. SIGNAL DESCRIPTIONS Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 3). Chip Enable (E2 - E0). These chip enable inputs are used to set the 3 least significant bits (b3, b2, b1) of the 7 bit device select code. These inputs may be driven dynamically or tied to VCC or VSS to establish the device select code. Write Control (WC). A hardware Write Control pin (WC), and a Protect Register, is provided on pin 7 of the M34W02. This feature is useful to protect a part or the entire contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIL) or disable (WC = VIH) write instructions to the protected memory area and to the Protect Register. When unconnected, the WC input is internally read as VIH and neither the protected memory area nor the Protect Register will be alterable.
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M34W02
DEVICE OPERATION I C Bus Background The M34W02 supports the I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The M34W02 is always a slave device in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the M34W02 continuously monitors the SDA and SCL signals for a START condition and will not respond unless a START condition is given. Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the M34W02 and the bus master. A STOP condition at the end of a Read sequence, after and only after a No-Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.
2
Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input. During data input the M34W02 samples the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation, the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Memory Addressing. To start communication between the bus master and the slave M34W02, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit. The 4 most significant bits of the device select code are the device type identifier, corresponding to the I2C bus definition. For this memory the 4 bits are fixed as 1010b to access the memory area and as 0110b to access the Protect Register. The following 3 bits identify the specific memory on the bus. They are matched to the external chip enable signals E2, E1, E0. Thus up to eight 2K memories can be connected on the same bus giving a memory capacity total of 16K bits. After a START condition any
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus, fc = 400KHz
20 VCC 16 RL RL
RL max (k)
12 MASTER 8
SDA SCL CBUS
CBUS 4 VCC = 5V 0 25 50 CBUS (pF) 75 100
AI01115
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M34W02
Table 5. Input Parameters (1) (TA = 25 C, f = 400 kHz )
Symbol CIN CIN ZWCL ZWCH tLP Parameter Input Capacitance (SDA) Input Capacitance (other pins) WP Input Impedance WP Input Impedance Low-pass filter input time constant (SDA and SCL) VIN < 0.3 VCC VIN < 0.7 VCC 5 500 200 500 Test Condition Min Max 8 6 20 Unit pF pF K K ns
Note: 1. Sampled only, not 100% tested.
Table 6. DC Characteristics (TA = 0 to 70C or -40 to 85C; VCC = 4.5V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VCC 0V VOUT VCC SDA in Hi-Z VCC = 5V, fC = 400kHz (Rise/Fall time < 10ns) VCC = 1.8V, fC = 400kHz VIN = VSS or VCC, VCC = 5V VIN = VSS or VCC, VCC = 5V, fC = 400kHz VIN = VSS or VCC, VCC = 1.8V VIN = VSS or VCC, VCC = 1.8V, fC = 400kHz VIL VIH VIL VIH VOL Input Low Voltage (SCL, SDA) Input High Voltage (SCL, SDA) Input Low Voltage (E0-E2, WC) Input High Voltage (E0-E2, WC) Output Low Voltage IOL = 3mA, VCC = 1.8V -0.5 0.7 VCC -0.5 VCC - 0.5 Min Max 2 2 2 1 100 300 30 100 0.3 VCC 6.5 0.5 6.5 0.4 Unit A A mA mA A A A A V V V V V
ICC
Supply Current
ICC1
Supply Current (Standby)
ICC2
Supply Current (Standby)
DEVICE OPERATIONS (cont'd) memory on the bus will identify the device code and compare the following 3 bits to its chip enable inputs E2, E1, E0. The 8th bit sent is the read or write bit (RW ), this bit is set to '1' for read and '0' for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time. If the memory does not
match the device select code, it will self-deselect from the bus and go into standby mode. Write Operations Following a START condition the master sends a device select code with the RW bit set to '0'. The memory acknowledges it and waits for a byte address, which provides access to the 256 bytes of the memory area. After receipt of the byte address, the memory again responds with an acknowledge and waits for the data byte.
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M34W02
Table 7. AC Characteristics (TA = 0 to 70C or -40 to 85C; VCC = 4.5V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol tCH1CH2 (1) tCL1CL2 tDH1DH2 tDL1DL2
(1) (1) (1)
Alt tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time
Parameter
Min
Max 300 300
Unit ns ns ns ns ns ns ns s s ns ns s
20 20 600 600 600 0 1.3 100 600 1.3 200 200
300 300
tCHDX (2) tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV tCLQX fC tW
Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Next Data Out Valid Data Out Hold Time Clock Frequency Write Time
900
ns ns
400 10
kHz ms
Notes: 1. Sampled only, not 100% tested. 2. For a reSTART condition, or following a write cycle.
Table 8. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 50ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Byte Write. In the Byte Write mode, after the device select code and the address, the master sends one data byte. If the addressed location is in a write protected area, the memory sends a NoACK and the location is not modified. If the addressed location is not write protected, the memory sends an ACK. The master terminates the transfer by generating a STOP condition. Depending on the 4 MSBs of the device select code, the Byte Write instruction can be used to modify a memory location (device select code 1010b) or can be used to access to the Protect Register contents (device select code 0110b). Page Write. The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the 4 most significant memory address bits (A7-A4) are the same. The master sends from one up to 16 bytes of data, which are
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.7VCC 0.3VCC
AI00825
0.2VCC
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M34W02
Figure 5. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE
tCLCH
tDXCX
tCHDH
tDHDL STOP & BUS FREE
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
tDHDL SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
AI00795
each acknowledged by the memory if the addressed row is not write protected. If the addressed row is write protected, each data byte is followed by a NoACK and the locations will not be modified. After each byte is transferred, the internal byte address counter (4 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter 'rollover' which could result in data being overwritten. Note that, for any byte or page write mode, the generation by the master of the STOP condition
starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request. Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table. Since the typical time is shorter, the time seen by the system may be reduced by an ACK polling sequence issued by the master.
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M34W02
Figure 6. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
The sequence is as follows: - Initial condition: a Write is in progress (see Figure 7). - Step 1: the master issues a START condition followed by a device select byte (1st byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, NoACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will respond with an ACK, indicating that the memory is ready to receive the second part of the incoming instruction (the first byte of this instruction was already sent during Step 1).
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Set the Protection using the Protect Register. The M34W02 has a software write protection function, with the use of a Protect Register, that allows a selectable memory area size to be defined as write protected. To activate the write protection feature, an address pointer has to be written into the Protect Register. When write protected by the Protect Register and the WC pin, the selected memory area will behave as a ROM area. The Protect Register is accessed by sending a write command with the 4 device type identifier bits of the device select code set to 0110b (see Figure 9), the E2-E1-E0 bits as applied on the E2-E1-E0 pins and regardless of the state of the WC signal.
M34W02
In this sequence, the address byte value is don't care and the Data byte is programmed in the protect register. The write protection is activated by putting the WC pin high (see Figure 9). The Protect Register is a 8 bit EEPROM register which contains a 7 bit row pointer (b6-b0) and 1 bit (b7), named Top/Bottom. When using the Protect Register, the EEPROM area will be divided in 2 different zone. The first zone is from location 00h to the pointed row with its 16 bytes included. The second zone is the rest of the memory to the top. Depending on the value of bit 7 of the Protect Figure 7. Write Cycle Polling using ACK Register, it is possible to write protect the first zone (b7=0) or the second zone (b7=1). As a row is 16 bytes long, it is possible to write protect from 16 bytes up to the entire 256 bytes with a step of 16 bytes (see Figure 9). The Protect Register contents can be write protected using the WC input pin (pin 7). When the WC input is read at VIH, it ensures that the Protect Register cannot be modified (device select code 0110xxxx not Acknowledged) and the write protected EEPROM area will behave as a ROM.
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by M34W02
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Byte Address
STOP
Proceed WRITE Operation
Proceed Random Address READ Operation
AI01963
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M34W02
DEVICE OPERATIONS (cont'd) b0 to b6: this is the row pointer value which contains the selected row number. This row number is used as a memory pointer which will determine the protected area size. b7: Top/Bottom: When b7=0 (WC=1), the protected area will be from location 00h to the pointed row (zone 1). When b6-b0 of the protect register are all 0, all the memory locations are not write protected. When b7=1 (WC=1), the protected area will be from the pointed row to the end of the memory (zone 2). When b6-b0 of the protect register are all 0, all the memory locations are write protected. On delivery, the Protect Register is set to 00h (all bits at '0'). This specific state allows the Protect Register to be programmed once even if the WC input is high. This feature is useful to program the Protect Register with the M34W02 soldered in the application. Pin 7 of the M34W02 can be directly connected to VCC. After and only after programming the Protect Register, even with the value 00h, the WC input (pin 7) will be activated by the M34W02: the Protect Register and the selected memory area will be write protected. It is possible to modify the write protected area by pulling the WC pin low (see Figure 9). To modify the Protect Register content, the WC input must be low. At this time, it is possible to modify all the 8 bits of the protect register (bit 7 included). This feature allows you to modify the protected area size and to modify the selected memory zone by changing the value of bit 7. Read Operations Read operations are independent from the state of the Protect Register and the WC input pin. On delivery, the memory contents is set at all "1's" (or FFh) and the Protect Register at all "0's" (or 00h). Current Address Read. The memory has an internal byte address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition,
Figure 8. Protected Area Size
M34W02 Memory F0h E0h FFh EFh
Row Number Not allowed 15
b6 b5 b4 b3 b2 b1 b0 0 0 0 0 1 0 0 1 0 1 0 1 0 1
20h 10h 00h
2Fh 1Fh 0Fh
3 2 1 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 0 0
1 0 1 0
AI01965
the master sends a device select code with the RW bit set to '1'. The memory acknowledges this and outputs the byte addressed by the internal byte address counter. This counter is then incremented. The master must NOT acknowledge the byte output and must terminate the transfer with a STOP condition. It is possible, when the WC input pin is low, to read the contents of the protect register. In this case, after the START condition, the device select code must have the 4 device type identifier bits set to 0110b. When the WC input pin is high, it is not possible to read the protect register. Random Address Read. A dummy write is performed to load the memory address into the address counter, see Figure 11. This is followed by another START condition from the master and the device select code is repeated with the RW bit set to '1'. The memory acknowledges this and outputs the byte addressed. The master must NOT acknowledge the byte output and must terminate the transfer with a STOP condition.
Table 9. Protect Register Bit Value
Bit Top / Bottom b7 Protect Register bits Protect Register bits values on delivery T/B 0 b6 rp6 0 b5 rp5 0 b4 rp4 0 ROW pointer b3 rp3 0 b2 rp2 0 b1 rp1 0 b0 rp0 0
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M34W02
Figure 9. Memory Protection
EXAMPLES OF THE PROTECT REGISTER AND THE "WC" INPUT PIN 16 15 ZONE 2 MEMORY AREA 5 4 3 2 1 3 Protect Register WC = 0: The complete EEPROM memory area can be modified WC = 1 and b7 = 0: The rows 1, 2, and 3 and the Protect Register are Write Protected ZONE 1 5 4 3 2 1 3 ZONE 1 Row Number 16 15 ZONE 2 5 4 3 2 1 3 ZONE 1
16 15 ZONE 2
WC = 1 and b7 = 1: The rows 4 to 16 and the Protect Register are Write Protected
AI01964
Figure 10. Write Modes Sequence in Non-Write Protected Area
ACK BYTE WRITE DEV SEL
ACK DATA IN
ACK
BYTE ADDR R/W ACK ACK
START
ACK DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR R/W
START
ACK DATA IN N
ACK
STOP
STOP
AI01941
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M34W02
Figure 11. Read Modes Sequence
ACK CURRENT ADDRESS READ DEV SEL NO ACK DATA OUT R/W
START
ACK RANDOM ADDRESS READ DEV SEL *
ACK DEV SEL *
STOP
ACK
NO ACK DATA OUT
BYTE ADDR
START
R/W
START
R/W
ACK SEQUENTIAL CURRENT READ DEV SEL
ACK
ACK
NO ACK
DATA OUT 1 R/W
DATA OUT N
START
ACK SEQUENTIAL RANDOM READ DEV SEL *
ACK DEV SEL *
ACK
ACK
BYTE ADDR
DATA OUT 1 R/W
START
R/W
ACK
NO ACK
DATA OUT N
STOP
START
AI01942
Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
Sequential Read. This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte output and MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automatically incre-
mented after each byte output. After a count giving the last memory address, the address counter will 'roll- over' and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the M34W02 waits for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the M34W02 terminates the data transfer and switches to a standby state.
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STOP
STOP
M34W02
ORDERING INFORMATION SCHEME Example: M34W02 - R MN 6 T
Operating Voltage blank W R 4.5V to 5.5V 2.5V to 5.5V 1.8V to 5.5V
Package BN PSDIP8 0.25mm Frame MN SO8 150mil Width DW TSSOP8 169mil Width
Temperature Range 1 6 0 to 70 C -40 to 85 C T
Option Tape & Reel Packing
Devices are shipped from the factory with the memory content set at all "1's" (FFh). For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you.
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M34W02
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm Typ A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 Min 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ inches Min 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150
Symb
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Drawing is not to scale.
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M34W02
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Typ A A1 B C D E e H h L N CP 1.27 Min 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ inches Min 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8
Symb
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Drawing is not to scale.
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M34W02
TSSOP8 - 8 lead Thin Shrink Small Outline
mm Typ A A1 A2 B C D E e H L N CP 0.65 0.05 0.85 0.19 0.09 2.90 4.30 - 6.25 0.50 0 8 0.08 Min Max 1.10 0.15 0.95 0.30 0.20 3.10 4.50 - 6.50 0.70 8 0.026 0.002 0.033 0.007 0.004 0.114 0.169 - 0.246 0.020 0 8 0.003 Typ inches Min Max 0.043 0.006 0.037 0.012 0.008 0.122 0.177 - 0.256 0.028 8
Symb
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Drawing is not to scale.
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M34W02
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1998 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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